1. Field of the Invention
The present invention relates to a lateral type transistor in which an emitter region, a base region and a collector region are formed in the lateral direction within the element forming region of an SOI (silicon on insulator) substrate formed by some suitable process such as a bonding process or the like and a manufacturing method thereof.
2. Description of the Prior Art
As a future VLSI (very large-scale integrated circuit), a bipolar transistor having an SOI structure has received considerable attention because the SOI structure can prevent a latch-up and reduce a parasitic capacitance by a complete separation of an insulating material.
In particular, a lateral type bipolar transistor having an SOI structure can reduce the parasitic capacitance substantially so that it can be realized as an ideal device as much as possible. At present, a BiCMOS LSI has received considerable attention because of its high packing density, lower power dissipation and high speed equivalent to that of a bipolar transistor. If, however, the vertical bipolar transistor and a CMOS transistor are combined, then a resultant transistor becomes complicated in structure, which leads to the increased cost due to the increase of process steps, a decrease of yield or the like.
In this case, considering a CMOS transistor having an SOI structure and a lateral type bipolar transistor having an SOI structure, most of the manufacturing processes of the CMOS transistor and the lateral type bipolar transistor can be made common, thereby making it possible to manufacture a high performance BiCMOS transistor by a very simple manufacturing method. Because of these advantages mentioned above, it is expected that the lateral bipolar transistor having an SOI structure will receive considerable attention from now on.
When a conventional lateral type bipolar transistor having an SOI structure is manufactured, a substrate having an SOI structure (hereinafter simply referred to as an SOI substrate) is produced first. The SOI substrate is manufactured as follows.
Initially, there are prepared a substrate 3 in which an N-type epitaxial layer 2 is grown on a P-type silicon substrate 1 as shown in FIG. 1A of the accompanying drawings and another substrate 6 in which a thermal oxide layer 5 is formed on the surface of a silicon substrate 4 as shown in FIG. 1B of the accompanying drawings. These two substrates 3 and 6 are bonded together while the surface of the epitaxial layer 2 and the surface of the thermal oxide layer 5 are being opposed to each other, thereby manufacturing a bonded substrate 7 shown in FIG. 2 of the accompanying drawings.
Then, as shown in FIG. 3 of the accompanying drawings, the end face of the substrate 3 is ground and polished. Finally, the substrate 3 is treated by a selective etching process composed of the etching action and the mechanical polishing process to thereby remove a silicon substrate 1. Thus, an SOI substrate 8 in which the silicon layer 2 is formed on the insulating layer 5 is obtained.
When the lateral bipolar transistor is fabricated on the SOI substrate 8, as shown in FIG. 4A of the accompanying drawings, a field insulating layer 9 is selectively formed by utilizing a selective oxidation method (LOCOS (local oxidation of silicon)). At that time, a silicon layer surrounded by the field insulating layer 9 becomes an element forming region 10.
As shown in FIG. 4B of the accompanying drawings, after a thin thermal oxide layer 11 formed on the element forming region 10 was partly removed by the etching process, an offset region is provided on the element forming region 10 and an N-impurity-doped polycrystalline silicon layer is formed. An SiO.sub.2 layer 13 of the same pattern is formed on the polycrystalline silicon layer 12. Thereafter, by the ion implantation technique of P-type impurity, e.g., Boron (BF.sub.2.sup.+), a P-type base region 14 is formed within the element forming region 10 at its portion in which the polycrystalline silicon layer 12 is not formed.
As shown in FIG. 5 of the accompanying drawings, a side wall formed of SiN layer, for example, is formed on the side wall of a bilayer film formed of the polycrystalline silicon layer 12 and an SiO.sub.2 layer 13. Thereafter, by the ion implantation technique of N-type impurity, e.g., Arsenic (As.sup.+), an N-type emitter region 16 is formed within the element forming region 10 m thereby obtaining an SOI lateral bipolar transistor (see "A Thin-Base Lateral Bipolar Transistor Fabricated on Bonded SOI" SC-9-8, pp. 216 to 217, autumn meeting feld by Institute of Society of Electronics, Information and Communication Engineers, 1991). In this case, the base is derived by means of a base deriving electrode region 17 continuously overgrown in the lateral direction as shown in a plan view of FIG. 6 of the accompanying drawings. The polycrystalline silicon layer 12 serves as a collector deriving electrode.
The above conventional SOI lateral bipolar transistor employs the bonded SOI substrate 8 so that a crystallizing property of the SOI substrate 8 itself is satisfactory. In addition, since the emitter region 16 and the base region 14 are formed by utilizing an LDD (lightly doped drain) structure of the MOS transistor, a base width Wb can be reduced and a cut-off frequency of f.sub.TMAX =4.5 GHz can be obtained.
In the conventional lateral type bipolar transistor, the base width Wb is determined by the width of the side wall 15 formed of the SiN layer. The width of the side wall 15 is determined by the thicknesses of the polycrystalline silicon layer 12 and the SiO.sub.2 layer 13 and the etching condition of the RIE process.
The polycrystalline silicon layer 12 and SiO.sup.2 layer 13 are generally formed by the CVD (chemical vapor deposition) method. When the layer is formed by the CVD method, a fluctuation of about 10% occurs in the thickness direction. Further, since a fluctuation of about 10% is caused by the etching process based on the RIE process, the width of the formed side wall 15 is also fluctuated considerably. As a result, control of the side wall width, i.e., base width Wb becomes unstable and a reduction of the base width Wb is unavoidably limited.
Furthermore, according to the conventional SOI lateral bipolar transistor, the base electrode is derived only from the longitudinal direction of the base region 14 so that a series resistance Rb of the base is increased, thereby decreasing the operation speed in a large current area.